This application claims the benefit of Japanese Patent Applications No.2001-210671 filed Jul. 11, 2001 and No.2002-101646 filed Apr. 3, 2002, in the Japanese Patent Office, the disclosures of which are hereby incorporated by reference.
1. Field of the Invention
The present invention generally relates to electronic circuit designing methods and apparatuses and storage media, and more particularly to an electronic circuit designing method and an electronic circuit designing apparatus for designing an electronic circuit such as large scale integrated circuits (LSIs), multi chip modules (MCMs) and printed circuit boards (PCBs), and to a computer-readable storage medium which stores a program for causing a computer to carry out such a designing of the electronic circuit.
2. Description of the Related Art
When designing an electronic circuit using computer-aided design (CAD), the design procedure includes a first step which determines the general layout and general wiring, a second step which inserts logic circuits into the circuit, a third step which edits the layout and wiring of the circuit, and a fourth step which analyzes the characteristics of the circuit and the wiring. The second and third steps are carried out based on design constraints related to the layout and the wiring. The design constraints are created by a skilled circuit designer (person) using various analyzing tools.
According to the conventional electronic circuit designing method, the design constraints are created by the circuit designer, as described above. For this reason, there is a first problem in that the design quality of the circuit is greatly dependent on the skill of the circuit designer. In other words, the design quality becomes inconsistent depending on the skilled level of the circuit designers, and the design time increases due to design corrections which need to be made depending on the skilled level of the circuit designer.
On the other hand, the circuit designer and the layout designer may be different. For this reason, when a circuit which satisfies the design constraints cannot be designed in the third step, the circuit designer and the layout designer must consult with each other and look over the design constraints again. However, such an operation of looking over the design constraints needs to be repeated many times in most cases, and there is a second problem in that the deign time is considerably increased thereby.